The present invention relates to an image processing apparatus and an image processing method.
In a field of image processing, real-time conversion of an image format is often required. Hardware is used in the real-time conversion of an image format; recently, however, format conversion by software executed by a CPU has been proposed.
There are now many applications requiring one piece of input image data to be simultaneously converted to a plurality of formats in real time for output. A video camera, for example, outputs one piece of image data obtained by photographing by the camera to multiple video media having different formats, such as a viewfinder, a recording tape, a liquid crystal panel, a television and the like.
Furthermore, many of recently spread digital televisions and liquid crystal panels have various formats, while the number of pixels of a CCD, which forms the camera, has been increased. Thus the entire system has become complicated.
In constructing such a system, a type, operation, and the like of a memory for retaining data are selected to be different for different systems. In addition, image formats have been diversified. Hence, not only a conventional memory access control unit but also an entire system including the memory access control unit has become very complicated in configuration.
Further, as described above, in order to realize control appropriate to the system, system design is required for each such system.
FIG. 16 is a block diagram showing a configuration of a memory control unit 119 in a conventional image processing apparatus. As shown in FIG. 16, the conventional memory control unit 119 includes: a first writing FIFO unit 401; a second writing FIFO unit 402; a third writing FIFO unit 403; a fourth writing FIFO unit 404; a first reading FIFO unit 405; a second reading FIFO unit 406; a third reading FIFO unit 407; a fourth reading FIFO unit 408; and a memory access control unit 419.
The first to fourth writing FIFO units 401 to 404, the first to fourth reading FIFO units 405 to 408, and a data retaining memory 117 are each connected to the memory access control unit 419. The first writing FIFO unit 401 is supplied with data DI1 and a synchronizing signal SI1. The second writing FIFO unit 402 is supplied with data DI2 and a synchronizing signal SI2. The third writing FIFO unit 403 is supplied with data DI3 and a synchronizing signal SI3. The fourth writing FIFO unit 404 is supplied with data DI4 and a synchronizing signal SI4.
The first reading FIFO unit 405 outputs data DO1 and a synchronizing signal SO1. The second reading FIFO unit 406 outputs data DO2 and a synchronizing signal SO2. The third reading FIFO unit 407 outputs data DO3 and a synchronizing signal SO3. The fourth reading FIFO unit 408 outputs data DO4 and a synchronizing signal SO4.
In the conventional memory control unit 119 as described above, the data DI1 to DI4 for different systems is written to the first to fourth writing FIFO units 401 to 404, respectively. The memory access control unit 419 temporarily stores the data in the data retaining memory 117. The first to fourth reading FIFO units 405 to 408 output the data stored in the data retaining memory 117 in response to synchronizing signals OC1 to OC4 supplied thereto, respectively.
An application that converts the format of image data and has a plurality of input and output systems as described above generally requires that one memory be accessible from a plurality of circuits for effective utilization of the memory.
In this case, in order to perform the access in real time, one method is conceivable in which a large FIFO memory is provided in a stage preceding the memory access control unit 419. However, this method increases development cost.
Further, when a method of controlling such access is to be devised, design, specification change and the like become difficult.